This invention relates to the fabrication of high density integrated non-volatile memory devices, and specifically to the fabrication of a self-aligned ferroelectric memory transistor
MFMOS ferroelectric devices have desirable characteristics as memory transistors, however, one of the most difficulties processes in MFMOS ferroelectric memory transistor fabrication is the step of etching the bottom electrode. The bottom electrode has to be selectively etched without etching through the thin oxide layer, typically located under the bottom electrode, and into the silicon substrate. The oxide layer underlying the bottom electrode may be either silicon dioxide, or a suitable high-k insulator. If the underlying substrate is inadvertently etched, it is impossible to form a good source/drain junction having adequate connections to the conductive channel of the transistor.
A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, including forming a p-well, depositing a first dielectric layer over the p-well, and forming a layer of n+ polysilicon over the first dielectric layer; forming shallow trenches for use in a shallow trench isolation process, wherein the shallow trenches extend through the polysilicon, the first dielectric layer, and about 500 nm of the substrate; depositing silicon oxide in the shallow trenches; removing the polysilicon except in active areas; depositing a bottom electrode on the polysilicon; forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; depositing a layer of silicon oxide, wherein the silicon oxide layer is between about 1.5 to 2.0 times the thickness of the gate stack; planarizing the silicon oxide layer to the level of the silicon nitride; removing the silicon nitride; forming a sidewall barrier layer by depositing a layer of barrier metal in a thickness of between about 5 nm to 30 nm; depositing a layer of ferroelectric material forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.
It is an object of the invention to provide a method fabricating a self-aligned MFMOS ferroelectric memory transistor.
Another object of the invention is to construct a ferroelectric stack and associated electrodes without contaminating the underlying structures.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.